This invention relates generally to the manufacture of semiconductor devices, and more specifically to an improved process for manufacturing silicon gate CMOS devices in which the silicon gate electrodes are doped independently of the source and drain doping.
The fabrication of CMOS semiconductor devices is a complicated process in which a large number of individual process steps must fit together in order to produce a reliable and manufacturable product. Each process step potentially increases the cost and complexity of the process and can lead to a decrease in the throughput or yield of the process. There has been, therefore, an effort to reduce the number of processing steps, especially photolithography steps, by combining functions, making certain process steps self aligning with respect to other process steps, and the like. The disadvantage of such reductions in the number of process steps, however, may be a loss in flexibility of the total process.
Always keeping in mind the concern for minimizing the number of process steps, however, additional steps are sometimes added to the process in order to improve the operating characteristics of the device being fabricated. For example, polycrystalline silicon electrodes and interconnection have been reduced in resistivity in order to improve the operating speed of the device. This is accomplished, in one process, by heavily doping the polycrystalline silicon with conductivity determining impurities. In the conventional process, however, the same doping operation is used to dope both the polycrystalline silicon and the source and drain regions in the underlying monocrystalline silicon substrate. Heavy doping in the polycrystalline silicon is inconsistent with the doping level and junction depth desired for the regions formed in the substrate. Relatively light doping in the polycrystalline silicon, which may be consistent with the desired doping level and junction depth in the source and drain regions, may cause unacceptable resistance in the polycrystalline silicon interconnection and from upper surface to lower surface of the polycrystalline silicon gate electrode. In accordance with an alternate process, the polycrystalline silicon regions in the semiconductor device are silicided with a metal silicide in order to reduce the resistivity. Although this may improve the conductivity along a polycrystalline silicon line, it does not necessarily improve the vertical conductivity in the polycrystalline silicon. The transconductance of the device is adversely affected by a high resistance in the vertical direction through the polycrystalline silicon as this introduces an unwanted or unacceptably high RC time constant. Additionally, it is known that conductivity determining impurities, especially N-type impurities, diffuse readily through silicided polycrystalline silicon. Thus N-type dopants in one portion of the circuit structure can rapidly diffuse through silicided polycrystalline silicon interconnecting lines to adversely dope the polycrystalline silicon gate electrode of an adjacent device. The doping in the polycrystalline silicon determines the gate-to-substrate work function and thus the threshold voltage of the device in question. The presence of N-type dopant, for example, in the gate electrode of a P-channel transistor causes an unwanted increase in the threshold voltage of that device.
In order to improve certain device characteristics, especially the resistance of the device to hot carrier injection (HCI) and the attendant reliability problems associated with HCI, many devices are fabricated using a lightly doped drain (LDD) structure. The process used to produce the LDD structure requires the formation of sidewall spacers on the side of the gate electrodes to space a heavily doped drain portion a predetermined distance away from the gate electrode. In the conventional process the width of the sidewall spacer is the same on all devices unless extra processing steps are used to produce different spacers on different devices. Accordingly, unless additional processing steps are used, the drain structure spacing on all devices using the spacers is the same.
Accordingly, a need existed for an improved process which would allow the independent doping of gate electrodes and source and drain regions in the substrate, which would improve the conductivity of the polycrystalline silicon, which would allow the silicidation of the polycrystalline silicon, and which would provide the flexibility of allowing different sidewall spacer widths on P-channel and N-channel transistors.
It is therefore an object of this invention to provide an improved process for fabricating CMOS devices having low polycrystalline silicon sheet resistivities.
It is the further object of this invention to provide an improved process for forming silicon gate CMOS devices in which the gate electrodes are doped independently of the source and drain regions.
It is yet another object of this invention to provide an improved silicon gate CMOS process having different sidewall spacer widths for N-channel and P-channel MOS transistors.
It is yet another object of this invention to provide an improved process for fabricating silicided silicon gate CMOS devices.